Multiplexing transceiver with 4 CSI2 inputs and a single CSI2 output

Overview

This IP multiplexes inputs from up to 4 CSI2 cameras, each with up to 4 data lanes, to a single CSI2 output stream, with up to 4 lanes. It comprises of existing VLSI PLus IP cores, optimized for CSI2 multiplexing, and glue logic

Key Features

  • Up to 4 CSI2 camera inputs
  • Each input is up to 4 data lanes
  • Output - 4 data lanes CSI stream

Benefits

  • Simple virtual-channel based multiplexing of CSI2 camera.

Block Diagram

Multiplexing transceiver with 4 CSI2 inputs and a single CSI2 output Block Diagram

Deliverables

  • Verilog RTL
  • SDC file

Technical Specifications

Maturity
N/A
Availability
NOW
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Semiconductor IP