Multi-channel Cable Modulator

Overview

The CMS0024 Multi-channel Cable Modulator encodes up to four separate transport streams for J83 or DVB-C. The resulting QAM symbols are filtered and up-converted, each channel to its own frequency division multiplex (FDM) sub channel. The IF channels are then combined output to the radio interface as a single I/Q sample stream for translation to the final RF frequency.

Although most designs will implement only one of the cable standards, it is possible to synthesise the core to support any combination of standards in a single device.

Multiple instances of CMS0024 may be used on an FPGA, sharing access to a single external RAM device. This would typically take the form of a fast SRAM (or possibly SDRAM through a suitable SDRAM controller).

Multi-core implementations typically employ separate DACs for each core with the resulting modulated baseband or IF carriers up-converted to the assigned RF frequency bands and combined to produce the wideband cable transmission signal.

Key Features

  • Compliant with DVB-C (EN 300 429); ITU J.83 Annexes A, B and C; DOCSIS 1.x, 2.0 and 3.0.
  • Scalable architecture supports 1 to 4 channels per core, and multiple instances per FPGA.
  • Modulation accuracy > 45dB (MER).
  • On-chip or off-chip interleaving RAM.
  • Variable symbol-rate interpolation.
  • Software selectable channel filter.
  • AD9857/AD9957/AD9789 interface and auto programming support.
  • AD9516/ADF4350 PLL programming support.
  • Extension core available for SPI/ASI interface with integrated PCR TS re-stamping, NULL TS packet removal/filtering and NULL/PRBS TS packet insertion.
  • Seamless integration with Altera ASI megacore when using SPI/ASI extension core.
  • Optional input and output TS rate estimation registers.
  • Optional noise interference source
  • Modes that are not required may be removed with synthesis options to generate a compact, efficient design.
  • Designed for very efficient FPGA implementation without compromise to the targeting of gate array or standard cell structures such as Altera HardCopy.
  • Supplied as a protected bitstream or netlist (Megacore for Altera FPGA targets).

Block Diagram

Multi-channel Cable Modulator Block Diagram

Deliverables

  • Implementation
    • Optimised for Altera.
    • Evaluation boards available.

Technical Specifications

Availability
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Semiconductor IP