MPEG-2 HD Decoder - Supports 1080p60. 4:2:2. 8-bit,

Overview

The MPEG-2 Decoder Core is a high performance and high quality solution video decompression engine targeted primarily at FPGAs. It is compliant with ISO/IEC 13818-2 (H.262) standards. The decoder design is fully autonomous and does not require any external processor to aid the decode operation. The IO interface comprises of an input FIFO and an output frame buffer. Decoded data can also be provided on a serial
bus with embedded sync information. The decoder requires single external DDR SDRAM to store reference pictures. The decoder solution is available either as a FPGA netlist or in source code format and can be customized to meet the requirements of end users.

Key Features

Standard: ISO/IEC 13818-2 (H.262)
Profiles: Simple, Main and 4:2:2
Video Resolutions: Up to 1920 x 1080
Frame Rate: Up to 60 fps
Bit rate: 100Mbps
Chroma Format: Monochrome, 4:2:0 & 4:2:2
Precision: 8 bits
Input Format: Elementary or Transport stream
Output Format: Decoded pictures in frame buffer. Optional serial
output with embedded sync information
FPGA: Xilinx Kintex Ultrascale, Kintex-7, Artix-7, Virtex-6 and Spartan-6. Altera devices are also supported. Contact us for the information.
FPGA Resources Numbers for 1920 x 1080p60, 422, 8-bit, 100 Mbps decoder.
FPGA - Kintex Ultrascale
LUTs - 9000
BRAMs - 42.5
DSPs - 65
This does not include memory controller, display controller and TS demultiplexer

Benefits

Fully standards compliant - tested with ITU-T & other industry standard test suites
Robust error handling, resilience & concealment.
Processes metadata related to closed captions & AFD.
Seamless switching between streams encoded with different settings including different resolutions, chroma formats and bit depths
Single chip solution with no processor requirement
Supports progressive and interlaced formats
Easy to integrate and hence faster time-to-market
Low resource utilization

Block Diagram

Applications

Broadcast
Video Contribution & Distribution decoders
Multi-format digital receivers (IRDs)
Video / Play-out Servers
High End Consumer Electronics
Test & Measurement Equipment’s
Aerospace & defense
Medical

Deliverables

Source Code or Netlist
Simulation Model
Hardware Test Platform
Build Scripts
Test Reports
User Manual
Design Documentation
Constraint Files
Test Benches
Support for one year

Technical Specifications

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