MPEG-1/2 + AAC Audio Decoder

Overview

The MPEG-1/2+AAC Audio Decoder (CWda99) is an audio IP core for decoding up to 6 audio channels in real-time.

This core contains the MPEG + AAC decoder software and the Coreworks processor based hardware audio engine platform (CWda3111).

The software is compiled into an image file (.bin) which can be automatically boot-loaded through one of the control interfaces (parallel AMBA APB or serial SPI) and run on the audio engine platform with simple parameters setting.

The program can be configured, controlled and monitored by means of a configuration, control, and status register file, accessed by the control interfaces.

The audio input and output interfaces uses a native parallel interface. Other standard audio interfaces, such as I2S/TDM and SPDIF are also available.

The interface to the external memory can be one of the following: AMBA AXI (for ASICs or Xilinx FPGAs), Avalon (for Altera FPGAs) or MIG (for Xilinx FPGAs).

The CWda3111 platform is an instance of the generic CWdaXYZ audio engine platform. Other platforms are available for a different number of audio channels (from 2 channels, up to 32 channels). Please contact us to select the best solution for your requirements.

Key Features

MPEG-1/2 and AAC decoders are compliant with the ISO/IEC 11172-3, 13818-7, and 14496-3 audio standards, using Fraunhofer IIS high quality software
Supported AAC formats: AAC-LC, HE-AAC, and HE-AAC v2
Supported MPEG formats: MPEG-1/2 Layers I and II
Supported channel modes for AAC: mono, dual mono, stereo, 2.1, 3.0, 3.1, 4.0, 5.0, and 5.1
Supported transport types for AAC: ADIF, ADTS, LATM, and LOAS
Supports multiple audio streams - limited to 6 audio channels in total (e.g. 3 stereo streams)
16-bit output audio resolution
Requires 6.9 MB of external memory
Configurable latency useful to synchronize with other sources (e.g. video)
Minimum latency: 1 frame assuming burst data input
Software interface protocol for control, configuration and monitoring
Parameter change while muting or repeating one frame
Real time operation @90 MHz for worst-case settings. Results for other settings can be provided upon request

Benefits

Low operation frequency
Low power consumption
Optimizable to fulfill different design specifications

Block Diagram

Deliverables

Verilog source code or FPGA netlist
Hardware datasheet
Program binary
Software manual
Implementation constraints
Simulation environment or evaluation board (optional)

Technical Specifications

Foundry, Node

All

Maturity

Silicon and FPGA proven

Availability

Now

TSMC

Pre-Silicon: 65nm GP , 90nm G , 130nm G

UMC

Pre-Silicon: 130nm

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