MMSE MIMO Detector

Overview

MIMO (Multiple Input Multiple Output) techniques are being used more and more in recent and upcoming standards since they drastically outperform traditional SISO (Single Input Single Output) techniques in terms of maximum throughput and range. This gain results from an increased spectral efficiency, lowering the overall system costs.

A MMSE MIMO detector is an integral part of a MIMO receiver. The MMSE detector IP core offers high throughputs even on low-cost FPGAs and convinces with a low implementation complexity at the same time. Its flexibility at design-time and run-time makes it the ideal fit for all kinds of MIMP applications.

Key Features

Adaptable to different transmitter/receiver antenna configurations (e.g., 2×2, 4×2 or 4×4).
Support for different modulation schemes at run-time (QPSK, 16-QAM, 64-QAM, 256-QAM)
QR decomposition included

Benefits

High throughput even on low-cost FPGAs (hundreds of Mbit/s)
Design-time configuration of throughput for optimal resource utilization
Low-power and low-complexity design
AXI4-Stream interface for simple integration
Consecutive MIMO symbols may have different modulations
Can be combined with further IP cores from the Creonic product portfolio.
Available for ASIC and FPGAs (AMD Xilinx, Intel)
Deliverable includes VHDL source code or synthesized netlist, VHDL testbench, and bit-accurate or floating point Matlab, C or C++ simulation model

Applications

WiFi (IEEE 802.11)
3GPP LTE
HSPA+
Powerline communication (ITU G.9963, Homeplug AV2)
Internet access lines (G.993.5 alias G.vector with VDSL vectoring)
Further MIMO applications

Deliverables

VHDL source code or netlist
HDL simulation model e.g. for Aldec’s Riviera-PRO
VHDL testbench
Bit-accurate Matlab, C or C++ simulation model
Comprehensive documentation

Technical Specifications

Availability

February 2013

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