Mixed-Mode Clock Manager (MMCM) Module
Overview
The MMCM primitive in Virtex®-6 parts is used to generate multiple clocks with defined phase and frequency relationships to a given input clock. The MMCM module is a wrapper around the MMCM_ADV primitive that allows the MMCM to be used in the EDK tool suite.
Key Features
- Wrapper around the MMCM_ADV primitive
- Configurable BUFG insertion
- Supports all MMCM_BASE and some MMCM_ADV features, as applicable to embedded system designs
Technical Specifications
Related IPs
- Digital Clock Manager (DCM) Module
- Aeonic Generate Clock Generation Module [PLL], 8x smaller than fractional analog solutions
- Inter-Integrated Circuit (I2C) Master Module
- Serial Peripheral Interface (SPI) Master Module
- Universal Asynchronous Receiver/Transmitter Module
- A/D Converter IP, 10 bits, 40Msps, UMC 0.18um Mixed-Mode process