Vendor: Xilinx, Inc. Category: PLL

Mixed-Mode Clock Manager (MMCM) Module

The MMCM primitive in Virtex®-6 parts is used to generate multiple clocks with defined phase and frequency relationships to a giv…

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Overview

The MMCM primitive in Virtex®-6 parts is used to generate multiple clocks with defined phase and frequency relationships to a given input clock. The MMCM module is a wrapper around the MMCM_ADV primitive that allows the MMCM to be used in the EDK tool suite.

Key features

  • Wrapper around the MMCM_ADV primitive
  • Configurable BUFG insertion
  • Supports all MMCM_BASE and some MMCM_ADV features, as applicable to embedded system designs

Files

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Specifications

Identity

Part Number
Mixed-Mode Clock Manager (MMCM) Module
Vendor
Xilinx, Inc.
Type
Silicon IP

Provider

Xilinx, Inc.
HQ: USA
Contact Xilinx, Inc.

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Frequently asked questions about PLL IP cores

What is Mixed-Mode Clock Manager (MMCM) Module?

Mixed-Mode Clock Manager (MMCM) Module is a PLL IP core from Xilinx, Inc. listed on Semi IP Hub.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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