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MIPI VGI Verification IP

Overview

The MIPI VGI Verification IP is compliant with version 0.9 of Draft MIPI VGI specification and verifies MIPI VGI Bus interfaces. It includes an extensive test suite covering most of the possible scenarios. It performs all possible protocol tests in a directed or a highly randomized fashion which adds the possibility to create the widest range of scenarios to verify the DUT effectively.

MIPI VGI Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

MIPI VGI Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

  • Compliant to version 0.9 of Draft MIPI VGI specifications.
  • Full MIPI VGI Host and Peripheral functionality.
  • Supports Point to Point, Full duplex communication.
  • Supports 2-wire Asynchronous and 3-wire Synchronous interface.
  • Supports Wide range of clock frequency up to 78MHZ.
  • Supports serializer and de-serializer.
  • Supports transmission latency with in permissible limits.
  • Supports two categories of communication.
    • vGPIO Logic-state exchange
    • Messaging exchange
  • Supports the following generic frame structures.
    • Serial stream length
    • Message stream length
  • Supports the concept of device classes according to the range of supported data rates.
    • Asynchronous
    • 4Mbps
    • Synchronous
    • Gear-1 (G1) – 32 KHZ to 26 MHZ
    • Gear-2 (G2) – 32 KHZ to 52 MHZ
    • Gear-3 (G3) – 32 KHZ to 78 MHZ Supports In-Band Flow control.
  • Supports In-Band Hard Reset.
  • Supports default configuration 2-wire PWM signaling.
  • Supports Bus-accurate timing.
  • Supports insertion and detection of various types of errors.
  • Notifies the testbench of significant events such as transactions, warnings, and protocol violations.
  • MIPI VGI monitor has built in coverage analysis.
  • MIPI VGI monitor checks for protocol errors and timing violations.
  • MIPI VGI Verification IP comes with complete testsuite to test every feature of MIPI VGI specification.

Benefits

  • Faster testbench development and more complete verification of MIPI VGI designs.
  • Easy to use command Interface simplifies testbench control and configuration of Host and Peripheral.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

Block Diagram

MIPI VGI Verification IP Block Diagram

Deliverables

  • Complete regression suite containing all the MIPI VGI testcases.
  • Examples showing how to connect various components, and usage of Host, Peripheral and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Technical Specifications

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