MIPI STP Synthesizable Transactor

Overview

Key Features

• Compliant with MIPI STP Specification version 2.0 and 2.2
• Supports STP interface
• Supports ATB interface
• Supports TPIU interface
• Supports a trace stream comprised of 4-bit frames
• Supports for merging trace data from up to 65536 independent data sources (Masters)
• Supports up to 65536 independent data Channels per Master
• Supports basic trace data messages that can convey 4, 8, 16, 32, or 64 bit wide data
• Supports Time-stamped data packets using one of several time stamp formats including
• Gray code
• Natural binary
• Natural binary delta
• Export buffer depth (legacy STPv1 timestamp that requires DTC support)
• Supports Data packet markers to indicate packet usage by higher-level protocols
• Supports Flag packets for marking points of interest (for higher-level protocols) in the stream
• Supports Packets for aligning time stamps from different clock domains
• Supports Packets for indicating to the DTC the position of a trigger event, which is typically used to control actions in the DTC
• Supports Packets for cross-synchronization events across multiple STP sources
• Supports for user-defined data packets
• Facilities for synchronizing the trace stream on bit and message boundaries
• Supports all types of error insertion and detection
• Invalid Time-stamp format
• Invalid opcode
• Invalid async pattern
• Invalid version

Benefits

• Compatible with testbench writing using SmartDV's VIP
• All UVM sequences/testcases written with VIP can be reused
• Runs in every major emulators environment
• Runs in custom FPGA platforms

Block Diagram



Deliverables

• Synthesizable transactors
• Complete regression suite containing all the MIPI STP testcases
• Examples showing how to connect and usage of Synthesizable Transactor
• Detailed documentation of all DPI, class, task and functions used in verification env
• Documentation also contains User's Guide and Release notes

Technical Specifications