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MIPI SPP Verification IP

Overview

The SmartDV Verification IP (VIP) for MIPI SPP provides an efficient and simple way to verify the MIPI SPP devices. The SmartDV Verification IP for MIPI SPP is fully compliant with version 1.0 Specification and provides the following features:

MIPI SPP Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

MIPI SPP Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

  • Supports version 2.0 Specification.
  • Full MIPI SPP Debug Test System (Master) and Target System (Slave) functionality.
  • Supports Independent, Full-Duplex Communication.
  • Supports dynamic sizing of SPTBs with following types.
    • Single packet per SPTB
    • Variable sized SPTB
    • Constant sized SPTB
  • Supports following SPP packets.
    • Full SPP
    • Tiny SPP
  • Supports following Opcodes,
    • Write System
    • Read System
    • Write SP Config
    • Read SP Config
    • Unblock SP Engine
    • Initialize SP Engine
    • Nop
    • Pad
    • Write Read System
    • Loop Trig System
  • Supports the normal and error response generation.
  • Supports the config registers and access space related config registers with register address of 32 bits.
  • Supports 32 access spaces.
  • Supports write and read system transactions upto 64 bit address width.
  • Supports the injection and detection for following errors.
    • Bad version error
    • Bad command & response sequence number error
    • Bad opcode in CE chck first state error
    • Bad position of special opcode error
    • Bad end of SPTB error
    • Bad opcode error
    • Bad signature error
    • Bad config TBC error
    • Bad config size error
    • Bad config address error
    • Bad config register error
    • Bad config write error
    • Bad config read error
    • Bad access space unavailable error
    • Bad access space non existent error
    • Bad access space disabled error
    • Bad access space busy error
    • Bad system size error
    • Bad system address error
    • Bad system TBC error
    • System timeout busy error
    • System timeout not busy error
    • Bad response type error
    • Invalid response type error
    • Invalid error type error
    • Invalid error code error
  • Supports JTAG Access Space.
  • Callbacks in DTS, TS and monitor for various events.
  • Monitor, Detects and notifies the test bench of all protocol and timing errors.
  • Status counters for various events in bus.
  • Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
  • Functional coverage of complete MIPI SPP specifications.
  • MIPI SPP Verification IP comes with complete testsuite to test every feature of MIPI SPP specification.

Benefits

  • Faster testbench development and more complete verification of MIPI SPP designs.
  • Easy to use command interface simplifies testbench control and configuration of master, slave and monitor
  • Simplifies results analysis.
  • Runs in every major simulation environment.

Block Diagram

MIPI SPP Verification IP Block Diagram

Deliverables

  • Complete regression suite containing all the MIPI SPP testcases.
  • Examples showing how to connect various components, and usage of Master, Slave and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Technical Specifications

Request Info

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