The System Power Management Interface is a two wire interface that connects the integrated power controller (PC) of a System-on-Chip (SoC) processor system with one or more Power Management Integrated Circuits(PMIC) voltage regulation systems.
MIPI SPMI Target Controller
Overview
Key Features
- Compliance as per MIPI Alliance Specifiction version 2.0
- Support SCLK frequency Low Speed - 32kHz to 15MHz
- Support SCLK frequency High Speed - 32kHz to 26MHz
- Supported command sequences are
- Register 0 Write
- Register Write
- Register Read
- Extended Register Write
- Extended Register Read
- Extended Register Write Long
- Extended Register Read Long
- Reset
- Sleep
- Wakeup
- Shutdown
- Support Bus Arbitration
- Support Parity Check
- Support of generate parity
- Register Access using command sequence
Block Diagram
Deliverables
- Verilog Source code.
- User Guide.
- IP Integration Guide.
- Simulation script.
- Synthesis script.
- Encrypted UVM Verification Testbench Environment.
- Basic Testsuite.