MIPI RFFE Post Silicon Validation IP provides a smart way to post silicon validation of the MIPI RFFE component of a SOC. MIPI RFFE Post Silicon Validation IP provides an smart way to post silicon validation of the MIPI RFFE bi-directional two-wire bus. The SmartDV's MIPI RFFE Post Silicon Validation IP is fully compliant with version 1.0,2.0,2.1 MIPI Alliance specification for RF Front-End Control Interface and provides the following features.
MIPI RFFE PSVIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
MIPI RFFE PSVIP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.