MIPI RFFE Master IP Core

Overview

The MIPI RFFE Master controller IP is a highly optimized and technology agnostic implementation of the MIPI RFFE v.3.1 standard targeting both ASIC and FPGA technologies. This IP is used to connect a digital RFIC to RF front end components, like Power Amplifiers (PA), Low-Noise Amplifiers (LNA), filters, switches, power management modules, Antenna Turner and Sensors, which are considered RFFE Slaves. It supports up to 15 slaves and 4 masters that can be connected through RFFE bus. This MIPI RFFE Master IP is backward compatible with MIPI RFFE components version 3.0, 2.1, 2.0 and 1.0.

The IP-core has been heavily tested in System Verilog random regression environment.

Key Features

Richly Featured
- Fully compliant with MIPI RFFE v3.0 Specification
- Supports all RFFE Slave commands
- Support Standard, Timed and Mappable Triggers
- Supports all USID Prgramming procedures: 1, 2 and 3
- Supports wide range of clock frequencies up to maximum 52 MHz
- Configurable number of type of registers
Solid
- UVM based Verification
- Lint/CDC checked
Easy to use
- Solid documentation including integration guide
- Easy to use RTL test environment
- No special software required
- Strong engineering support for bring-up
Silicon Agnostic
- Targeting both ASICs and FPGAs

Block Diagram

Deliverables

The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual, Release Note and Quick Start Guide
- Simulation Environment, including Simple Testbed, Test case, Test Script
- Basic RTL Test Bench
- Synthesis Scripts
- Synopsys Lint and CDC Waivers
- Synopsys CDC SGDC Files
- Synopsys Constraint Files

Technical Specifications

Availability

available

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