IP Catalog > Interface IP > Interconnect IP > MIPI IP > MIPI PHY IP > MIPI M-PHY IP > MIPI M-PHY v3.1 IP in TSMC(12/16nm, 28nm, 40nm, and 55nm)

MIPI M-PHY v3.1 IP in TSMC(12/16nm, 28nm, 40nm, and 55nm)

Overview

MIPI M-PHY is a serial interface technology with high bandwidth capabilities, which is particularly developed for mobile applications to obtain low pin counts along with excellent power efficiency. As a MIPI Alliance contributor and leading Interface IP provider, M31 provides silicon-proven and low-power M-PHY in various process nodes. The M-PHY IP is optimized for UFS (Universal Flash Storage) applications, follows MIPI M-PHY v4.1 spec, supports a wide range of high-speed (HS) and low-speed (LS) data transfer, and complies with the RMMI interface for seamless integration with upside controllers. Moreover, M31 also provides various lane configurations for the M-PHY IP to meet different bandwidth requirements.

Key Features

  • Supports RMMI interface for applications such as UNIPRO protocol (UFS, CSI-3, DSI-2) and DigRF
  • High speed gears, HS-G1A/B, HS-G2A/B and HS-G3A/B with scalable power consumptions
  • Burst mode CDR with short sync length (< 16SI)
  • Low speed PWM Gears from G1 to G4 with ultra-low power consumptions
  • Supports reference-less function during low-speed operation
  • Common lane configuration facilitates the lane scalability
  • Low latencies to switch to/from different power states
  • Supports multiple signal amplitudes
  • Supports internal loopback BIST functions for at-speed mass production testing
  • Certified with ASIL-B of ISO 26262

Technical Specifications

Foundry, Node
12nm, 16nm, 28nm, 40nm, and 55nm process
SMIC
Silicon Proven: 40nm LL , 55nm LL
TSMC
Pre-Silicon: 7nm
Silicon Proven: 12nm , 16nm , 28nm HPCP , 40nm LP , 55nm LP
UMC
Pre-Silicon: 130nm
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