MIPI I3C Controller

Overview

Controller IP for the MIPI I3C interface

Compliant with the MIPI® I3C® specification and legacy compatible with the I2C specification, the Controller IP for MIPI I3C is engineered to quickly and easily integrate into any mobile embedded SoC device and expand sensor communication capabilities with better performance and power efficiency. The MIPI I3C Controller contains the capability to be either the Initiator/Host or the Target on the I3C bus.

Key Features

  • Support for Multiple Transmission Modes with Single Data Rate (SDR) and High Data Rate (HDR)
  • Support for I3C Common Command Code
  • Dynamic address assignment (DAA) support

Benefits

  • Superior Performance-to-Power Ratio: Compared to established sensor interfaces - I2C, SPI
  • Complete Solution: Contains the capability to be either the Initiator/Host/M or the Target/S on the I3C bus
  • Supports Legacy Interfaces: I2C mode supported

Block Diagram

MIPI I3C Controller Block Diagram

Technical Specifications

Maturity
Silicon Proven
×
Semiconductor IP