MIPI I3C Basic v1.1.1 specifications with Host Controller Interface v1.1 specification

Overview

The I3C (Improved Inter-Integrated Circuit) is the successor of the I2C bus. Keeping the best assets from its elder brother, the I3C has major improvements in use and power, and performance. The Core uses just two pins and consumes a fraction of the energy, reducing cost and complexity while allowing multiple sensors from different vendors to be easily interfaced with a controller or application processor.

DCD maintains backward compatibility, enabling a smooth transition from I2C to I3C and simple implementation. The newest Core offers a flexible multi-drop interface between a host processor and peripheral sensors, to support the growing usage of sensors in embedded systems. The same I3C standardizes sensor communication, reduces the number of physical pins used in sensor system integration, and supports low-power, high-speed, and other critical features that are currently covered by I2C and SPI.

Key Features

Conforms to MIPI I3C v1.1 specifications
MIPI Manufacturer ID: 0x03B3
Dynamic Addressing while supporting Static Addressing for Legacy I2C Devices
Legacy I2C messaging
I2C-like Single Data Rate messaging (SDR)
Master operation with FIFO:

Master transmitter
Master receiver

Supports flexible transmission speed modes:

FAST-PLUS (up to 1000 kb/s)
SDR (up to 12,5 Mb/s)

Configurable FIFO size up to 256 Bytes
Configurable SDA/SCL glitch filter
Software programmable SDA/SCL bus timings
Multi-master systems supported
Interrupt generation
Allows operation from a wide range of input clock
frequencies (build-in 12-bit clock timer)
Configurable interface allows easy connection to standard
bus interfaces: APB, AHB, 8051, 80251, others
Support for in-band interrupts
Support for I3C common command codes
Dynamic address assignment (DAA) support
Command queue support
Low power management support
Fully interoperable with third-party I3C master and slave
solutions
Fully synthesizable, static synchronous design with
positive edge clocking and synchronous reset
Available system interface wrappers:

AMBA – APB / AHB / AXI Bus
Altera Avalon Bus
Xilinx OPB Bus

Applications

Smartphones, tablets and laptops,
IoT
Medical, health & fitness,
Autonomous vehicles and ADAS,
Embedded microprocessor boards,
Low-power applications,
Communication systems etc

Deliverables

HDL Source Code
Testbench environment

Automatic Simulation macros
Tests with reference responses

Synthesis scripts
Technical documentation
12 months of technical support

Technical Specifications

Availability

Now

TSMC

Pre-Silicon: 130nm G
Silicon Proven: 130nm G

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