This is a DPHY IP compliant to the “MIPI Alliance Spec for D-PHY v1.2”, which consists of 1-Clock and 4-Data lanes. Data lane0 supports HS support and ULPS in the forward direction, and supports LP Escape modes (LPDT, Trigger, ULPS) and Turnaround in both forward and reverse direction; Other Data lanes support HS and LP Escape modes(LPDT, Trigger, ULPS) in the forward direction. Each lane supports 2.5Gbps in High-Speed mode and 10Mbps/lane in Low-Power escape mode. The target applications are CSI-2 host and DSI device physical layers.
MIPI DPHY-RX
Overview
Key Features
- Data rate per lane: High-Speed mode 80M~2.5G bps, Low-Power mode 10Mbps
- Silicon proven in GlobalFoundries 22FDX process
- Compliant to the MIPI D-PHY spec v1.2
- Lane type:1 clock + 4 data(D0 is bi-dir)
- Support for DPHY Ultra Low Power State
- On-chip differential 100Ω terminations with calibration
- Support for SUB-LVDSRX mode
- Built-in self test function
- Supply voltage: 1.8V±10%, 0.8V±10%
- Junction temperature range: -40°C~25°C~125°C
- Support wire-bond and flip-chip package type
Block Diagram
Technical Specifications
Foundry, Node
Silicon proven in GlobalFoundries 22FDX process
Maturity
Silicon proven
GLOBALFOUNDRIES
Pre-Silicon:
22nm
FDX
SMIC
Pre-Silicon:
28nm
,
55nm
G
,
110nm
G
Samsung
Pre-Silicon:
28nm
LPP