MIPI DigRF Verification IP

Overview

MIPI DigRF Verification IP is compliant with MIPI DigRF specification and verifies DigRF devices. DigRF Verification IP is developed by experts who have worked on complex protocols before.

MIPI DigRF Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

MIPI DigRF Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Supports 1.2 MIPI DIGRF Specification.
Supports both Data and Control frames
Supports frames nesting
Supports up to four lanes
Supports distribution and merging data over lanes
Supports programmable sync pattern and length
Supports LS,HS1,HS2 modes
Supports HIBERNATE mode
Supports LOOPBACK and CLOCK TEST mode
Supports byte striping
Supports ARQ scheme(NACK only)
Supports ARQ scheme disable
Supports frames retransmission
Supports dummy frames retransmission
Supports lane insertion
Includes the MIPI M-PHY VIP for physical layer verification

Automatic Link Training
Low speed and High speed operation

Supports various types of frame errors

CRC error
Wrong CRI error
Various fields corruption error

Supports RMMI 10/20/40 Bit interfaces
Support following 8b/10b error insertion and detection

Invalid K character injection
Injection of disparity errors
Wrong K character injection
Corruption of Marker characters

Monitor,Detects and notifies the testbench of all protocol and timing errors.
Supports constraints Randomization.
Status counters for various events in bus.
Callbacks in transmitter and receiver for various events.
MIPI DigRF Verification IP comes with complete test suite to test every feature of MIPI DigRF specification.
Functional coverage for complete MIPI DigRF features.

Benefits

Faster testbench development and more complete verification of MIPI DigRF designs.
Easy to use command interface simplifies testbench control and configuration of Tx,Rx and monitor
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the MIPI DigRF testcases.
Examples showing how to connect various components, and usage of Tx,Rx and Monitor.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes.

Technical Specifications

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