MIPI D-PHY TRx 5nm

Overview

The MIPI D-PHY IP is a hardmacro PHY for CSI RX or DSI TX. IO pads and ESD structures are included. Extensive built-in self test features such as loopback and scann support. It offers a cost-effective and low-power solution.

Key Features

  • Samsung Foundry 5nm low power enhanced (LN11LPP) CMOS device technology
  • 1.8V±5%, 1.2V±5%, 0.8/0.9V±5% power supply
  • Fully supports MIPI D-PHY v1.2 HS/LP/ULPS Tx/Rx (Backward Compatible with previous versions)
  • Supports 80-2500Mbps in D-PHY HS mode
  • Global operation timing parameters control

Benefits

  • Low power consumption, small area
  • Supports both overdrive (0.9V) and normal (0.8V) power
  • Support for various lane configurations
  • Built-in self-test feature capable of producing and checking PRBS random pattern
  • Highly validated structure in various processes

Block Diagram

MIPI D-PHY TRx 5nm Block Diagram

Applications

  • Mobile, Automotive, IoT, DDI, TCON, etc

Deliverables

  • FE-Common: MODEL, TB, LEF, LIBERTY, ATPG, SIPI
  • BE-Common: CIR, GDS, DRC, LVS, DFMC
  • DOC-Common: Datasheet, User Guide, Test Guide, Supplement Guide, PLL Datasheet, PLL Calculator

Technical Specifications

Foundry, Node
Samsung Foundry SF5E
Maturity
Silicon Proven
Availability
Now
Samsung
Silicon Proven: 5nm
×
Semiconductor IP