MIPI D-PHY Rx IP, Silicon Proven in TSMC 16FFC

Overview

The MIPI D-PHY RX IP Core fully adheres to the D-PHY specification, version 1.2. It supports both the Display Serial Interface (DSI) and the MIPI Camera Serial Interface (CSI-2) protocols. The RX PHY comprises four data lanes and one clock lane.

The D-PHY includes a digital backend for managing I/O operations and an analog frontend for generating and receiving electrical level signals, incorporating an intrinsic resistor that is automatically terminated.

Key Features

Compliant to MIPI Alliance Standard for
D-PHY specification Version 1.2
Supports standard PPI interface compliant to MIPI Specification
Supports synchronous transfer at high speed mode with a bit rate of 80-2500 Mb/s
Supports asynchronous transfer at low power mode with a bit rate of 10 Mb/s
Supports ultra-low power mode, high speed mode and escape mode
Supports one clock lane and up to four data lanes
Data lanes support transfer of data in high speed mode
Supports error detection mechanism for sequence errors and contentions
Supports contention detection
Configurable skew option for each Clock and Data lanes
Silicon Proven in TSMC 16FFC.

Block Diagram

Deliverables

GDSII & layer map
Place-Route views (.LEF)
Liberty library (.lib)
Verilog behaviour model
Netlist & SDF timing
Layout guidelines, application notes
LVS/DRC verification reports

Technical Specifications

Maturity

In Production

Availability

Immediate

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