MIPI D-PHY Rx IP, Silicon Proven in GF 55LP
Overview
Version 1.2 of the D-PHY specification is fully complied with by the MIPI D-PHY Analog RX IP Core. Both the MIPI Camera Serial Interface (CSI-2) and Display Serial Interface (DSI) protocols can be used. This RX PHY is configured with one clock channel and four data lanes. The D-PHY comprises of a digital back end for managing I/O operations and an analogue front end for sending and receiving electrical level signals. The intrinsic resistor is automatically terminated.
Key Features
- Compliant to MIPI Alliance Standard for D-PHY specification Version 1.2
- Supports standard PPI interface compliant to MIPI Specification
- Supports synchronous transfer at high-speed mode with a bit rate of 80-2500 Mb/s
- Supports asynchronous transfer at low power mode with a bit rate of 10 Mb/s
- Supports ultra-low power mode, high-speed mode and escape mode
- Supports one clock lane and up to four data lanes
- Data lanes support transfer of data in high-speed mode
- Supports error detection mechanism for sequence errors and contentions
- Supports contention detection
- Configurable skew option for each Clock and Data lanes
- Testability for TX, RX and PLL
- Silicon Proven in GF 55 LPe.
Block Diagram
Deliverables
- GDSII & layer map
- Place-Route views (.LEF)
- Liberty library (.lib)
- Verilog behaviour model
- Netlist & SDF timing
- Layout guidelines, application notes
- LVS/DRC verification reports
Technical Specifications
Maturity
In Production
Availability
Immediate
Related IPs
- MIPI D-PHY Tx IP, Silicon Proven in GF 55LP
- DDR3/ DDR3L Combo PHY IP - 1600Mbps (Silicon Proven in UMC 40LP)
- DDR4/ LPDDR4/ DDR3L PHY IP - 3200Mbps (Silicon Proven in TSMC 12FFC)
- DDR4/ LPDDR4/ DDR3L PHY IP - 1866Mbps (Silicon Proven in TSMC 28HPC+)
- MIPI D-PHY Rx IP, Silicon Proven in TSMC 7FF
- MIPI D-PHY Rx IP, Silicon Proven in TSMC 12FFC