MIPI D-PHY

Key Features

• Compliant with the MIPI D-PHY spec v2.5
• Fully integrated hard macro with lane control and interface logic
• Up to 1.5 Gbps per lane with upgradable option to 2.5 Gbps per lane
• Supports PHY Protocol Interface (PPI)
• Low-power escape modes and ultra low-power state modes

Technical Specifications