The Foresys MIPI Core provides a fast path to integrating Image Sensors or other MIPI connected devices into a wide variety of products based on Altera devices. The MIPI CSI2 Rx core is designed to convert MIPI data from an image sensor into an Avalon Streaming Video interface.
MIPI CSI2 Receiver
Overview
Key Features
- Provides Compatible MIPI D-Phy v1.1 physical layer using FPGA LVDS/LVCMOS IO and passive network
- Supports CSI-2 protocol for unidirectional data transfer
- Compatible with D-PHY Configured for 1 clock and 4 data lanes
- Intended for per-lane clocks rates up to 1 Gbps, depending on device speed grade
- Verifies CSI-2 header ECC field
- Verifies CSI-2 data CRC
- Transmits Avalon Streaming Video
- Optionally converts to 640×480 in RGB_888 format by simultaneously scaling and demosaicing
Block Diagram
Technical Specifications
Related IPs
- MIPI CSI-2 V3 RECEIVER INTERFACE IP
- MIPI CSI-2 Controller Core
- MIPI CSI-2 Receiver v2.0 Controller IP, Compatible with MIPI C-PHY & D-PHY
- MIPI CSI-2 Receiver v1.1 Controller IP, Compatible with MIPI C-PHY & D-PHY
- MIPI CSI-2 Receiver v1.3 Controller IP, Compatible with MIPI C-PHY & D-PHY
- MIPI CSI-2 Receiver for FPGA