IP Catalog > Interface IP > Interconnect IP > MIPI IP > MIPI Controller IP > MIPI CSI-3 IP > MIPI CSI-3 Verification IP

MIPI CSI-3 Verification IP

Overview

MIPI CSI-3 is a new generation of camera serial interface, expanding on the capabilities of CSI-2. By using a multipurpose link based on a common protocol stack (UniPort-M), CSI-3 provides higher bandwidth over fewer pins, with better power per bit efficiency than CSI-2. The SmartDV's MIPI CSI-3 Verification IP is fully compliant with version 1.2 MIPI Alliance specification for camera serial Interface 3 and provides the following features.

MIPI CSI-3 Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

MIPI CSI-3 Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

  • Supports Version 1.2 MIPI CSI-3 Specification
  • Supports transmission of Image frame
  • Supports transmission of Attribute packets
  • Supports Data transmission on multiple Virtual Channels
  • CAL provides support for camera configuration, camera control and data transport
  • Includes Proven MIPI UniPro and M-PHY bfm components for lower layer verification
  • M-PHY supports various transmission speed steps and ranges from 0.01 Mbps up to 5.8 Gbps per Lane
  • Supports all lane configuration
  • Supports implementation of standalone ISPs
  • Supports interleave the streams
  • Supports all CSI-2 legacy data formats
  • Supports following error insertion and detection
    • All MIPI MPHY errors
    • Disparity errors
    • Invalid code group errors
    • All Unipro errors
    • Invalid frame formats
    • L2 Credit violation
    • Cport buffer violation
    • All LSS errors
    • No response error injection
    • CRC errors
    • Reserve field error injection
    • Over and undersize errors
    • Lane mapping and disconnection error
    • All CSI-3 erros
    • Data type errors
    • Over and undersize errors
    • Malformed packet errors
    • Attribute errors
  • Supports compressed image data
  • The CCI device supports all four different read operations
    • Single read from random location
    • Sequential read from random location
    • Single read from current location
    • Sequential read from current location
  • The CCI device supports all two different write operations
    • Single write to random location
    • Sequential write starting from random location
  • The CCI supports the following register width
    • 8-bit
    • 16-bit
    • 32-bit
    • 64-bit
  • Monitor, Detects and notifies the testbench of all protocol and timing errors
  • Supports constraints Randomization
  • Status counters for various events in bus
  • Callbacks in transmitter and receiver for various events
  • MIPI CSI-3 Verification IP comes with complete test suite to test every feature of MIPI CSI-3 Version 1.0 specification.
  • Functional coverage for complete MIPI CSI-3 features

Benefits

  • Faster testbench development and more complete verification of MIPI CSI-3 designs.
  • Easy to use command interface simplifies testbench control and configuration of Tx,Rx and monitor
  • Simplifies results analysis.
  • Runs in every major simulation environment.

Block Diagram

MIPI CSI-3 Verification IP Block Diagram

Deliverables

  • Complete regression suite containing all the MIPI CSI-3 testcases.
  • Examples showing how to connect various components, and usage of Tx,Rx and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Technical Specifications

Request Info

Related IPs

×
Semiconductor IP