The Qualitas CSI-2 RX Controller offers high-speed serial connectivity between host processors and camera modules. Fully compliant with MIPI CSI-2 v2.0, this IP includes Receiver (Rx) capabilities over 4 D-PHY data lanes or 3 C-PHY data trios, with lane configurability to meet varying camera bandwidth requirements.
The IP supports all video pixel formats and provides optional video coordinate generation with Hsync, Vsync, and Video Data Enable (VDE). Additionally, it detects all packet-level and protocol decoding-level errors, ensuring data integrity.
Compliant with the CSE v1.0 specification, this IP includes functional safety features, making it ideal for automotive applications. It has undergone rigorous design verification through VIP function testing, ensuring reliable performance.
MIPI CSI-2 RX Controller
Overview
Key Features
- Compliant with the following specifications:
- MIPI CSI-2 Specification v2.0
- MIPI CSE Specification v1.0
- MIPI D-PHY Specification v2.1, 1 to 4 D-PHY data lanes
- MIPI C-PHY Specification v1.2, 1 to 3 C-PHY data trios
- APB Specification v3.0
- Supports D-PHY or C-PHY based on user configuration
- Provides lane merging, error detection and correction, virtual channel detection, programmable data extraction, and embedded data separation
- Supports all packet-level errors and protocol decoding-level errors
- Supports the following pixel formats:
- Raw7/8/10/12/14/16/20/24/28
- RGB444/555/565/666/888
- 8/10-bit YCbCr 4:2:0, 8-bit Legacy YCbCr 4:2:0, 8/10-bit YCbCr 4:2:2
Benefits
- Low power consumption
- Small footprint
- Complete function verification through VIP
Block Diagram
Applications
- Mobile, Automotive, AI, Security, AR/VR, etc
Deliverables
- Encrypted RTL source code
- Lint/CDC report
- Testbench
- Synthesis script
- Datasheet, User Guide
Technical Specifications
Maturity
Development IP
Availability
1Q 25