MIPI C-PHY v1.0 D-PHY v1.2 RX 2 trios/2 Lanes - TSMC N5 1.2V, North/South Poly Orientation

The integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for mobile, automotive, artificial intelligence (AI), and IoT applications. The PHY, for FinFET processes and compliant with the MIPI C-PHY and D-PHY specifications, operates at 6.5Gb/s per lane and 6.5Gs/s per trio respectively for a maximum speed of 44.5Gb/s. The C-PHY/D-PHY addresses energy requirements by supporting low-power state modes and delivering below 1.2pJ/bit at the maximum speed. The PHY offers built-in test capabilities, including pattern generator, logic analyzer, and loopback modes covering all circuits. The C-PHY/D-PHY IP interoperates with the vendor’s ASIL B Ready ISO 26262 certified CSI-2 and DSI/DSI-2 controllers which support key features of the latest MIPI display and camera specifications.