MIPI 4.1 M-PHY HS Gear 4

Overview

MIPI M-PHY HS Gear 4 IP is compliant with the MIPI serial communication protocol for use in mobile systems where performance, power, and efficiency are key criteria. It is the foundation for several upper layer protocols which manage complex data transfer functions. Each of these protocols is optimized for its particular purpose, such as data storage, data transfer, display, camera, memory sharing, and radio interface. Scalability and modularity are also important features of the MIPI M-PHY, as these features allow designers to more easily adapt to evolving system and application requirements.

Key Features

Supports high speed data transfer G4A/B and backward compatible
Multi-lane compatible
Supports 4 reference clocks as per MIPI 4.1 specification
PWM G1-G7 Signalling for Low Speed [LS] data
Supports LS burst, HS burst, STALL, SLEEP, HIBERN8 states
Supports squelch detection
In-built reference-less oscillator to support PWM operation
Supports all power down states
2 lane configuration to support 23.32Gbps or independent lanes
Supports Receiver Detect
Auto-Calibration of termination resistance
Programmable internal/external loopback modes between Tx and Rx.
Standby / power down mode
Modular design
Low silicon surface
Operating temperature -40oC to 125oC
Available in TSMC 28nm HPC/HPC+,TSMC 55nmLP& GP TSMC 65GP

Benefits

Supports MIPI CSI-3, MIPI DigRF, MIPI LLI, and MIPI UniPro
Adopted by

PCI SIG for M-PCIe
USB IF for SSIC

Supports Electrical Idle presentation with fast Electrical Idle Entry and Exit

Block Diagram

Applications

Mobiles
Tablets
Laptops
PCs
Wearables
Cameras
Storage

Deliverables

GDS II Layouts
LEF abstracts
CDL netlists
Liberty timings
Verilog description

Technical Specifications

Foundry, Node

TSMC 28nm HPC/HPC+,TSMC 55nm LP& GP TSMC 65GP

Maturity

CAD proven solution

Availability

Now

TSMC

Pre-Silicon: 28nm HPC , 28nm HPCP , 55nm GP , 55nm LP , 65nm GP
Silicon Proven: 28nm HPC

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