Perceptia’s DeepSub™ pPLL02 is a general purpose all digital PLL featuring low-jitter and compact area suitable for many clocking applications at frequencies up to 2GHz. It is suitable as a clock source for moderate speed microprocessor blocks and other logic.
To give SoC designers the maximum flexibility in building complex multi-domain clock systems, pPLL02F is very small and low power. pPLL02F integrates easily into any SoC design and includes all the views and models required by back end flows.
The pPLL02F is built using Perceptia’s all digital PLL technology. This robust technology delivers identical performance regardless of PVT conditions. It consumes a small fraction of the area of an analog PLL whilst maintaining comparable performance.
Perceptia further provides integration support and offers customization and migration services.
Minimum-area low-power clocking PLL (1st gen)
Overview
Key Features
- - Super small: 80 x 80 microns!
- - Very low power: 12-mW
- - Broad frequency range: 2-GHz
- - Fast lock
- - Preprogrammed loop filter
- - Scan testable
- - Decoupling caps for lower jitter
Block Diagram
Technical Specifications
Foundry, Node
65 - 180-nm
Availability
Now
GLOBALFOUNDRIES
Pre-Silicon:
90nm
,
90nm
LP
,
130nm
,
130nm
HP
,
130nm
LP
,
130nm
LV
,
180nm
,
180nm
LL
,
180nm
LL
,
180nm
LP
,
180nm
LP
Silicon Proven: 65nm LPe
Silicon Proven: 65nm LPe
SMIC
Pre-Silicon:
90nm
G
,
90nm
LL
,
110nm
G
,
130nm
G
,
130nm
LL
,
130nm
LV
,
150nm
G
,
150nm
LV
,
160nm
G
,
160nm
LL
,
180nm
G
,
180nm
LL
Silterra
Pre-Silicon:
90nm
,
130nm
Silicon Proven: 180nm
Silicon Proven: 180nm
TSMC
Pre-Silicon:
80nm
,
80nm
GT
,
80nm
HS
,
85nm
,
90nm
FS
,
90nm
FT
,
90nm
G
,
90nm
GOD
,
90nm
GT
,
90nm
LP
,
90nm
zzz
,
110nm
G
,
110nm
HV
,
110nm
LVP
,
130nm
,
130nm
G
,
130nm
LP
,
130nm
LV
,
130nm
LVOD
,
150nm
G
,
150nm
LV
,
160nm
G
,
160nm
LP
,
180nm
,
180nm
E
,
180nm
ELL
,
180nm
FG
,
180nm
G
,
180nm
LP
,
180nm
LV
,
180nm
ULL
UMC
Pre-Silicon:
80nm
,
90nm
G
,
90nm
LL
,
90nm
SP
,
110nm
,
130nm
,
150nm
,
162nm
,
180nm