MIL STD 1773 Verification IP

Overview

The MIL STD 1773 Verification IP is compliant with MIL STD 1773 specification and verifies MIL STD 1773 interfaces. It includes an extensive testsuite covering most of the possible scenarios. It performs all possible protocol tests in a directed or a highly randomized fashion which adds the possibility to create the widest range of scenarios to verify the DUT effectively.

MIL STD 1773 Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

MIL STD 1773 Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Compliant with MIL STD 1773 Standard.
Supports Bus Controller (i.e,BC), Remote Terminal (i.e,RT) and Bus Monitor (i.e,BM) operation.
Supports Single/Dual/Quad channel, dual redundant bus communication modules.
Supports configurable length of word length, default 20 bits.
Supports configurable length of data bits, default 16.
Supports configurable message length per transfer.
Supports following encoding/decoding types.
- NRZ coding
- Manchester II bi-phase coding
- Partial tri-level Manchester II bi-phase coding (i.e,PTMBC)
- Extended Manchester II bi-phase coding with beginning-stopping flags (i.e,EMBC-BSF)
Supports single or multi bus control.
Supports following message formats.
- Controller to terminal
- Terminal to controller
- Terminal to terminal
- Broadcast
- System control
Glitch insertion and detection
Supports up to 31 remote terminals.
Supports all types of errors insertion/detection as given below:
- Command word sync error
- Data word sync error
- Status word sync error
- Command word parity error
- Data word parity error
- Status word parity error
- NRZ or Manchester encoding error
- Bi-phase encoding error
- Low bi-phase encoding error
- High bi-phase encoding error
- Oversize data word error
- Undersize data word error
- Extra data words error
- Less data words error
- Various illegal command errors
- Inter message gap error
- Terminal response timeout error
On-the-fly protocol and data checking
Supports constraints Randomization.
Status counters for various events on bus
Supports bus accurate timing and timing checks.
Callbacks in Bus controller and Remote terminal for various events.
Built in functional coverage analysis
Notifies the testbench of significant events such as transactions, warnings and protocol violations.
FIFO depth programmable
MIL STD 1773 Verification IP comes with complete test suite to test every feature of MIL STD 1773 specification.

Benefits

Faster testbench development and more complete verification of MIL STD 1773 designs.
Easy to use command interface simplifies testbench control and configuration of Bus Controller and Remote Terminal.
Simplifies results analysis.
Runs in every major simulation environment

Block Diagram

Deliverables

Complete regression suite containing all the MIL STD 1773 testcases.
Examples showing how to connect various components and usage of Bus Controller, Remote Terminal and Monitor.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes.

Technical Specifications

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