The GR1553B core implements the MIL-STD-1553B (Notice 2) data bus protocol, with ability to serve as Bus Controller (BC), Remote Terminal (RT) or Bus Monitor (BM).
The core is connected to the MIL-STD-1553B bus via a dual transceiver interface (txP/N/en, rxP/N/en). On the system side, the core connects to the AMBA bus as an AHB master for DMA transfers and an APB slave for register access. The core uses a separate 20 MHz clock for the MIL-STD-1553B codec, and runs at any AMBA clock frequency from 10 MHz and upwards.
Mil-Std-1553B/AS15531 Interface
Overview
Key Features
- General
- Implements the MIL-STD-1553B (Notice 2) and SAE AS15531 data bus
- All transfer types supported, including RT-to-RT and broadcast transfers
- Dual-redundant bus support
- Continuous loop-back checking of transmitted MIL-STD-1553B data
- AMBA (Rev 2.0) AHB master interface, 16-bit aligned data buffers
- Bus Controller
- Automated transfer list with allocated time slots
- Synchronized start of transfer list with external pulse
- Automatic retries on same or alternating buses
- Secondary transfer list for best-effort, low priority transfers
- Optional interrupt generation at pre-defined points in transfer list
- Configurable RT response timeout, up to 44 μs
- Remote Terminal
- Flexible software interface allowing customizable buffering setups
- Auto wrap-around subaddress capable
- Time-stamping of transfers
- Programmable per subaddress maximum transfer size and transmit/receive/broadcast enable
- Interrupt generation on selected subaddresses
- Dedicated output that pulses on reception of a synchronize mode code
- Bus Monitor
- Ring buffer log
- Filter on address, subaddress, mode codes
- Can run in parallel with BC or RT
Deliverables
- FPGA/ASIC netlist
- Stand-alone testbench
- Optional plug and play interface for GRLIB IP library
- User's manual
- Driver for RTEMS and VxWorks
Technical Specifications
Availability
Now