MIL STD 1553 Controller IIP

Overview

MIL STD 1553 interface provides full support for the MIL STD 1553 synchronous serial interface, compatible with MIL STD 1553B specification. Through its MIL STD 1553 compatibility, it provides a simple interface to a wide range of low-cost devices. MIL STD 1553 IIP is proven in FPGA environment. The host interface of the MIL STD 1553 can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

MIL STD 1553 Controller IIP is supported natively in Verilog and VHDL

Key Features

Compliant with MIL STD 1553B specification
Supports Remote terminal, Bus Controller and Bus monitor
Supports configurable length of word length, default 20 bits
Supports configurable length of data bits, default 16 bits
Supports configurable message length per transfer
Supports various mode code and broadcast commands
Supports Manchester II Bi-phase encoding
Bus Controller Features
- Fully compliant with specs
- Fully programmable Bus Controller
- Bus Controller has 32-bit time count options
- Programmable Status Set
- Message Format Check
- Programmable Inter-Message Gap Time
- Programmable Message Timeout
- Passed full BC validation testing by 3rd party
Remote Terminal Features
- Fully compliant with specs
- Programmable different buffer mode for all Subaddress
- Sub address based illegal command declaration
- Optional temporary buffer
- Passed full RT validation testing by 3rd party
Bus Monitor Features
- Fully compliant with specs
- Monitors all frames on bus and timestamps
- Passed full RT validation testing by 3rd party
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple interface allows easy connection to microprocessor/microcontroller devices

Benefits

Single site license option is provided to companies designing in a single site.
Multi sites license option is provided to companies designing in multiple sites.
Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

Block Diagram

Deliverables

The MIL STD 1553 is available in Source and netlist products.
The Source product is delivered in plain text verilog.If needed VHDL,SystemC code can also be provided.
Easy to use Verilog Test Environment with Verilog Testcases
Lint, CDC, Synthesis, Simulation Scripts with waiver files
IP-XACT RDL generated address map
Firmware code and Linux driver package
Documentation contains User's Guide and Release notes.

Technical Specifications

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