M31 memory compilers are designed with high industrial standard which provides the memory solutions for density, power, and performance optimization. M31 memory compilers are using industry leading techniques to help customers to achieve their various SOC projects.
Meanwhile, M31 Memory Compiler IP was certified with ASIL D of ISO 26262 on April, 2019.
Memory Compiler in TSMC(16nm,22nm,28nm,40nm,55nm,90BCD+,110nm,152nm,180BCD)
Overview
Key Features
- Synchronous read/write operation
- Low leakage current and lower operation power consumption
- Minimum metal layer requirement: 4/3 metal layers
- High density layout structure and small area design
- Flexible geometry optimization for aspect ratio requirement
- Provide power trunk with ring/ringless type instance macro
- Provide built-in options for yield/performance optimization
- Support BIST integration
- Support repaired system solution
Technical Specifications
Foundry, Node
TSMC(16nm,22nm,28nm,40nm,55nm,90BCD+,110nm,152nm,180BCD)
GLOBALFOUNDRIES
Silicon Proven:
28nm
,
28nm
SLP
,
40nm
LP
,
130nm
,
180nm
SMIC
Silicon Proven:
40nm
LL
,
55nm
LL
TSMC
Pre-Silicon:
16nm
Silicon Proven: 22nm , 28nm HPCP , 40nm LP , 55nm ULP , 55nm ULPEF , 90nm G , 110nm G , 180nm G
Silicon Proven: 22nm , 28nm HPCP , 40nm LP , 55nm ULP , 55nm ULPEF , 90nm G , 110nm G , 180nm G
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