1G to 50G Single-Port MACsec Engine with TSN support

Overview

The MACsec-IP-161 is a versatile MACsec solution for silicon devices that require plug-and-play MACsec processing for an Ethernet port at full line rate. It provides classification, transformation and statistics for the IEEE802.1AE standard MACsec.

Additionally, it supports VLAN-in-clear use cases, IEEE802.3br preemption and Cisco ClearTags protocols. The IP-161 is available in numerous configurations optimized for desired throughput range, number of secure connections and features set. Supplied with software support, the MACsec-161 is the ideal solution for TSN Ethernet PHYs, switches, automotive, 5G SoCs and many other Ethernet-connected applications.

How the MACsec-IP-161 works

The MACsec-IP-161 engine provides complete MACsec processing for a port. A port may process a single stream or an interleaved stream of IEEE802.3br fragments. It contains flexible classifier with a table of programable rules with the programmable actions. The transformation engine supports all features and ciphers of the standard MACsec and VLAN-in-clear extension. The processing results are reflected in the MACsec compliant statistics as additional non-standard counters. The MACsec-IP-161 engine is a basis for building various use cases. Beside traditional point-to-point and point-to-multipoint use cases, it is also deployed in protecting carrier networks with bypass/drop/protect policy that is controlled per VLAN EVC. The engine can be delivered with full Cisco ClearTags support that can be used in combination with preemption. The MACsec-IP-161 can be used in combination with external classifier and accepts secure channel pointer or packet bypass indication.

Key Features

  • Packet Interface
    • Cut-through FIFO interface with frame interleaving for IEEE802.3br
    • 128-bit wide
    • External classification inputs
    • SOP and EOP pass-through bus for side-band information
    • Lowest and fixed-latency modes
  • SA and classification scaling
    • SA (16 to 256)
    • TCAM rules (16 to 512)
  • Control Interface
    • Simple 32-bit interface
    • Interrupts
  • Protocol Support
    • Full IEEE 802.1AE-2018 compliance
    • IEEE 802.1AE
    • IEEE 802.1AEbn
    • IEEE 802.1AEbw
    • IEEE 802.1AEcg
    • MACsec with up to 4x VLAN-in-clear
  • FIPS 140-2 CAVP ready
    • Support for basic AES and AEC-GCM transformations

Benefits

  • Complete and compliant MACsec Packet Engine for rates from 1GbE to 50GbE with TSN support (including IEEE803.2br).
  • All IEEE MACsec standards supported (incl. IEEE802.1AE-2018). Optional Cisco ClearTags.
  • Supplied with the Driver Development Kit to accelerate time to market. Rambus offers MACsec Toolkit for IEEE 802.1X key management

Deliverables

  • Packages
    • Silicon IP
    • Driver Development Kit
  • Complete Documentation
    • Hardware integration guide
    • Hardware and software reference manuals
    • Programming guides
    • IP-XACT Register description
  • Tools and Scripts
    • Verilog for synthesis and simulation
    • All scripts and support files needed for standard EDA tool flows

Technical Specifications

Foundry, Node
Any
Maturity
Silicon Proven
Availability
Now
TSMC
Silicon Proven: 7nm , 16nm , 28nm , 40nm G
×
Semiconductor IP