IP Catalog > Memory & Libraries IP > I/O Library IP > High-speed IP > LVDS IP > LVDS Receiver PHY

LVDS Receiver PHY

Overview

The LVDS Receiver IP is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolution. The LVDS Receiver IP converts the LVDS data stream back into 35 bits of CMOS data with a variety of LCD panel controllers.

The receiver LVDS clock operates at rates from 25 MHz to 150 MHz, At an incoming clock rate of 150MHz, each LVDS input line is running at a bit rate of 1.05Gbps.

 

Key Features

  • Converts 5-pair LVDS data stream into parallel 35 bits of CMOS data
  • Compatible with the TIA/EIA-644 LVDS standards
  • Supports up to 1.05Gbps data rate for UXGA
  • On-chip DLL requires no external component
  • Power-down control function
  • Negative clock edge for data output
  • Core area: 0.4134mm^2
  • Wide dot clock range: 25 ~ 150MHz suited for VGA, SVGA, XGA, SXGA, SXGA+ and UXGA
  • Function compatible with the National DS90CF386
  • Silicon Proven in 22,28,55,65,130n,180n from SMIC, Global Foundries and Samsung
  • On chip 100Ω termination resistor. Can be disable.
  • Power consumption:
    •   71.8mW@1.05Gbps, prbs7 pattern

Block Diagram

LVDS Receiver PHY Block Diagram

Technical Specifications

Foundry, Node
GSMC 0.18um
Maturity
Pre-Silicon
SMIC
Pre-Silicon: 28nm HK , 55nm G , 65nm LL , 130nm LL , 180nm G
Request Info

Related IPs

×
Semiconductor IP