IP Catalog > Memory & Libraries IP > I/O Library IP > High-speed IP > LVDS IP > LVDS/ MIPI Combo PHY IP, Silicon Proven in SMIC 40LL

LVDS/ MIPI Combo PHY IP, Silicon Proven in SMIC 40LL

Overview

The MIPI-LVDS Combo Tx IP is designed for chips that perform high bandwidth data communication while operating at low power consumption. It can be easily fabricated and implemented in a GVI, LVDS or MIPI DSI system. For GVI/LVDS system, Macro consists of multi-transmitter channels and one SU unit. The speed of transmitter macro is up to 4.0Gbps and can be configured to GVI (CML) or LVDS mode. For MIPI DSI system, a DSI configuration includes a Clock Lane Module and four Data Lane Modules.

Key Features

  • GVI
  • Support data rate: 0.5Gbps~4.0Gbps
  • configurable reference clock frequency
  • Per-lane 10-bit/9-bit/8-bit/7-bit parallel interface
  • Support Spread Spectrum clock generation: up to
  • ±5000ppm@31.5KHz
  • AC coupling, 75nF~200nF at both ends and one end in TX near-end.
  • One shared PLL for all lanes
  • Individually power down for each lane
  • Support 0~9dB programmable 2-tap FFE (Feed forward equalization)
  • LVDS
  • Support data rate: 0.25Gbps~2.0Gbps
  • Configurable reference clock frequency
  • Per-lane 10-bit/9-bit/8-bit/7-bit parallel interface
  • DC coupling
  • One shared PLL for all lanes
  • Individually power down for each lane
  • Support 0~9dB programmable 2-tap FFE (Feed forward equalization)
  • DSI
  • One Clock Lane Channel and four Data Channels
  • Data Channel 0 : Bi-directional with Low-Power RX (LP-RX) and Low-Power CD (LP-CD)
  • Channel 1-4: High-Speed TX (HS-TX) and a Low-Power TX (LP-TX)
  • HS operation rate : 187.5Mbps~1.5Gbps
  • LP operation rate: 10Mbps
  • DC Coupling
  • One shared PLL for all lanes
  • Contention detection module
  • Common Features
  • Embedded BIST
  • Support wire bonding package
  • Reliability
  • Life Time : 20 years, with average temperature up to 100degC : 10 years, with average temperature up to 110degC
  • Availability : 100%
  • ESD(HBM) : over 2000V
  • ESD(CDM) : over 500V
  • Latch-up : >100mA

Deliverables

  • Application Note / User Manual
  • Behavior model, and protected RTL codes
  • Protected Post layout netlist and Standard
  • Delay Format (SDF)
  • Frame view (LEF)
  • Metal GDS (GDSII)
  • Test patterns and Test Documentation

Technical Specifications

Maturity
In Production
Availability
Immediate
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