Implementation of the older drafts standard IEEE P1619 required the NIST standard AES cipher in the LRW mode for encryption (AES-LRW). Note that the new drafts of the P1619 call for a different mode, XTS-AES (see our XTS cores). The LRW1 AES core is tuned for storage applications at the data rates of 3 Gbps and higher. The LRW2 family of cores covers a wide range of area / throughput combinations, allowing the designer to choose the smallest core that satisfies the desired clock/throughput requirements. All LRW cores contain the base AES core AES1 and are available for immediate licensing. LRW3 family is similar to LRW2, but supports 256-bit AES keys and no-penalty key and IV changes.
The design is fully synchronous and available in both source and netlist form.
LRW-AES Core
Overview
Key Features
- Small size: LRW1 starts at 30,000 ASIC gates at throughput of 12.8 bits per clock
- Synthesized for 600+ MHz clock speeds (70+ Gbps throughput for LRW2-128)
- Completely self-contained: does not require external memory
- Supports Liskov-Rivest-Wagner encryption and decryption (LRW-AES a.k.a. AES-LRW)
- Includes LRW-AES encryption, LRW-AES decryption, key expansion and data interface
- No penalty for key and IV changes (back-to-back operation)
- 128+128 bit LRW keys supported. 256+128 bit key supported by LRW3.
- Easily parallelizable for higher data rates
- Test bench provided
Block Diagram
Applications
- Storage encryption
Deliverables
- HDL Source Licenses
- Synthesizable Verilog RTL source code
- Test bench (self-checking)
- LRW-AES vectors for testbenches
- Expected results
- User Documentation
- Netlist Licenses
- Post-synthesis EDIF
- Testbench (self-checking)
- LRW-AES vectors for testbenches
- Expected results
- Place & Route script
Technical Specifications
Short description
LRW-AES Core
Vendor
Vendor Name
Foundry, Node
TSMC, UMC 0.13
Availability
Now