LPDDR5X Assertion IP

Overview

Key Features

• Specification Compliance
  • Supports 100% of LPDDR5X protocol draft JEDEC specification and JESD209-5B specification
  • Supports all the LPDDR5X commands as per the specs
  • Supports following device modes,
  • X8 Mode
  • X16 Mode
  • Supports WCK2CK Sync operation
  • Supports burst length 16 and 32
  • Supports for all mode registers programming
  • Supports Read DBI and Write DBI operation
  • Supports for Hybrid Refresh mode and Refresh credit mode
  • Supports for Write zero CAS command
  • Supports all data rates as per specification
  • Supports system ECC function.
  • Supports CA parity
  • Checks for following
  • Check-points include power on, Initialization and power off rules,
  • State based rules, Active Command rules,
  • Read/Write Command rules etc,
  • All timing violations
  • Supports deep sleep mode
  • Supports power down mode and refresh operation
  • Supports ECC and CRC
  • Quickly validates the implementation of the LPDDR5X draft JEDEC specification and JESD209-5B specification
  • Bus-accurate timing for min, max and typical values
  • Constantly monitors LPDDR5X behavior
  • Protocol checker fully compliant with LPDDR5X draft JEDEC specification and JESD209-5B specification
• Assertion IP features
  • Assertion IP includes:
  • System Verilog assertions
  • System Verilog assumptions
  • System Verilog cover properties
  • Synthesizable Verilog Auxiliary code
  • Support Master mode, Slave mode, Monitor mode and Constraint mode
  • Supports Simulation mode (stimulus from SmartDV LPDDR5X VIP) and Formal mode (stimulus from Formal tool)
  • Rich set of parameters to configure LPDDR5X Assertion IP functionality

Benefits

• Runs in every major formal and simulation environment.

Block Diagram

Deliverables

• Detailed documentation of Assertion IP usage.
• Documentation also contains User's Guide and Release notes.

Technical Specifications