With sophisticated architecture and advanced technology, the Vendor provides LPDDR5 IP solution with high performance and low power. In advanced process nodes, the Vendor could offer both controller and PHY IPs. In architecture, it supports Multiport AMBA AXI interface, configurable port number and support asynchronous or synchronous AXI port. For PHY interface, it will integrate DFI compatible design. One de-skew PLL is embedded inside the PHY to improve jitter performance.
LPDDR5 IP solution
Overview
Key Features
- Support LPDDR5 up to 6400Mbps
- Support Channel equalization with 1-tap DFE
- Support single-ended mode on CK, WCK and read DQS below 3200Mbps
- Support Link ECC for RDQS and DM
- Support DVFS/Data Copy/Write X
- Support DDRPHY loopback test for high speed test
- Fully PINMUX easy for PKG/PCB routing
- Support mask write, write/read DBI
- Support Hardware based DDR frequency switch (DFS), and DFI 1:1/1:2/1:4 programmable with frequency, trade-off latency and power
Block Diagram
Deliverables
- Datasheet (Including Integration Guideline, Interface PINs, clock and reset description, all training flows etc.) (DDRMC & DDRPHY)
- Register Map files (register address and function description), timing calculation sheet (DDRMC & DDRPHY)
- Timing lib/db, Layout Frame (.LEF) (DDRPHY)
- Encrypted RTL and Netlist, SPEF/SDF (DDRPHY)
- Top Level GDS (DDRPHY)
- RTL Code & SDC Constraints (DDRMC)
- Verification environment and cases (testbench, DDRIO Verilog model, initial flow, training flow, bandwidth access, DFT pattern etc. (DDRMC & DDRPHY)