LPDDR2 / LPDDR3 / DDR3 / DDR3L / DDR3U / DDR4 Combo I/O Pad Set

Overview

The LPDDR2/3_DDR3/4 library includes the combo driver/receiver cells with embedded power cells, the driver impedance calibration cell, and a full complement of support cells for both single-ended and differential signaling for LPDDR2, LPDDR3, DDR3, DDR3L, DDR3U, and DDR4 applications. Also included is a full complement of power, corner and spacer cells to assemble a complete pad ring by abutment. An included rail splitter allows multiple power domains to be isolated in the same pad ring while maintaining continuous VDD/VSS for robust ESD protection.

Key Features

  • Full DDR4 capability
  • Data rates – 1600 MT/s, 1866 MT/s, 2133 MT/s, 2400 MT/s
  • Full DDR3 / DDR3L / DDR3U capability
  • Data rates – 800 MT/s, 1066 MT/s, 1333 MT/s, 1600 MT/s, 1866 MT/s, 2133 MT/s
  • Full LPDDR3 capability
  • Data rates – 1333 MT/sec, 1600 MT/sec
  • Full LPDDR2 capability
  • Data rates – 466 MT/sec, 1066 MT/sec
  • ESD Protection:
  • JEDEC compliant
  • o 2KV ESD Human Body Model (HBM)
  • o 200 V ESD Machine Model (MM)
  • o 500 V ESD Charge Device Model (CDM)
  • Latch-up Immunity:
  • JEDEC compliant
  • Tested to I-Test criteria of ± 100mA @ 125°C

Deliverables

  • a. Physical abstract in LEF format (.lef)
  • b. Timing models in Synopsys Liberty formats (.lib and .db)
  • c. Calibre compatible LVS netlist in CDL format (.cdl)
  • d. GDSII stream (.gds)
  • e. Behavioral Verilog (.v)
  • f. Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
  • g. Databook (.pdf)
  • h. Library User Guide - ESD Guidelines (.pdf)

Technical Specifications

Foundry, Node
GLOBALFOUNDRIES 28nm
Maturity
Silicon Proven
Availability
Available Now
GLOBALFOUNDRIES
Silicon Proven: 28nm HPP , 28nm LPH , 28nm SLP , 40nm LP , 65nm , 65nm LP , 65nm LPe
TSMC
Pre-Silicon: 65nm G
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Semiconductor IP