LPDDR Memory Model

Overview

LPDDR Memory Model provides an smart way to verify the LPDDR component of a SOC or a ASIC. The SmartDV's LPDDR memory model is fully compliant with standard LPDDR Specification and provides the following features. Better than Denali Memory Models.

LPDDR Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

LPDDR Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Supports LPDDR memory devices from all leading vendors.
Supports 100% of LPDDR protocol standard JESD209B and JESD209A-1.
Supports all the LPDDR commands as per the specs.
Supports up to 2GB device density
Supports the following devices.

Supports all speed grades as per specification.
Quickly validates the implementation of the LPDDR standard JESD209B and JESD209A-1.
Supports Programmable CAS latency.
Supports Programmable burst lengths: 2, 4, 8 and 16.
Checks for following

Check-points include power up, initialization and power off rules,
State based rules, Active Command rules,
Read/Write Command rules etc.
All timing violations.

Supports for All Mode registers/Control programming.
Supports for Extended Mode register programming.
Supports for the following Burst Types,

Sequential
Interleave

Supports for Burst order.
Supports for Write data Mask.
Supports for Power Down features.
Supports for Deep Power Down features.
Supports for Auto Precharge option for each burst access
Supports for Auto Refresh and Self Refresh Modes
Supports for input clock stop and frequency change.
Supports for full-timing as well as behavioral versions in one model.
Supports for all timing delay ranges in one model: min, typical and max.
Optional Partial Array Self Refresh and Temperature Compensated Self Refresh
Constantly monitors LPDDR behavior during simulation.
Protocol checker fully compliant with LPDDR Specification JESD209B and JESD209A-1.
Model detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
Built in functional coverage analysis.
Supports Callbacks, so that user can access the data observed by monitor.

Benefits

Faster testbench development and more complete verification of LPDDR designs.
Easy to use command interface simplifies monitor control and configuration.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the LPDDR testcases.
Complete UVM/OVM sequence library for LPDDR controller.
Examples showing how to connect and usage of Model.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes.

Technical Specifications

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