IP Catalog > Interface IP > Memory Interface IP > LPDDR IP > LPDDR/mDDR IP > LPDDR/mDDR Controller IP > LPDDR Assertion IP

LPDDR Assertion IP

Overview

LPDDR Assertion IP provides an efficient and smart way to verify the LPDDR designs quickly without a testbench. The SmartDV's LPDDR Assertion IP is fully compliant with standard LPDDR Specification.

LPDDR Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

LPDDR Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

  • Specification Compliance
    • Supports all signal level checks including X detection
    • Supports LPDDR memory devices from all leading vendors.
    • Supports 100% of LPDDR protocol standard JESD209B and JESD209A-1.
    • Supports all the LPDDR commands as per the specs.
    • Supports up to 2GB device density
    • Supports the following devices.
    • X16
    • X32
    • Supports all speed grades as per specification.
    • Quickly validates the implementation of the LPDDR standard JESD209B and JESD209A-1.
    • Supports Programmable CAS latency.
    • Supports Programmable burst lengths: 2, 4, 8 and 16.
    • Checks for following
    • Check-points include power up, initialization and power off rules,
    • State based rules, Active Command rules,
    • Read/Write Command rules etc.
    • All timing violations.
    • Supports All Mode registers/Control programming.
    • Supports Extended Mode register programming.
    • Supports the following Burst Types,
    • Sequential
    • Interleave
    • Supports Burst order.
    • Supports Write data Mask.
    • Supports Power Down features.
    • Supports Deep Power Down features.
    • Supports Auto Precharge option for each burst access
    • Supports Auto Refresh and Self Refresh Modes
    • Supports full-timing as well as behavioral versions in one model.
    • Supports all timing delay ranges in one model: min, typical and max.
    • Optional Partial Array Self Refresh and Temperature Compensated Self Refresh
    • Constantly monitors LPDDR behavior during simulation.
    • Protocol checker fully compliant with LPDDR Specification JESD209B and JESD209A-1.
  • Assertion IP features
    • Assertion IP includes:
    • System Verilog assertions
    • System Verilog assumptions
    • System Verilog cover properties
    • Synthesizable Verilog Auxiliary code
    • Support Master mode, Slave mode, Monitor mode and Constraint mode.
    • Supports Simulation mode (stimulus from SmartDV LPDDR VIP) and Formal mode (stimulus from Formal tool).
    • Rich set of parameters to configure LPDDR Assertion IP functionality.

Benefits

  • Runs in every major formal and simulation environment.

Block Diagram

LPDDR Assertion IP Block Diagram

Deliverables

  • Detailed documentation of Assertion IP usage.
  • Documentation also contains User's Guide and Release notes.

Technical Specifications

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