The Low Power Wide Range PLL addresses markets and applications that demand very low power and optimized for area efficiencies. In addition, consumer devices have restrictions on supply voltage due to battery restrictions or board restrictions. The PLLs are designed for standard digitallogic processes and implement robust design techniques to work in noisy SoC environments. The PLLs can address a large portfolio of applications, ranging from non-integer clock multiplication to programmable clock synthesis for multi-clock generation.
The PLL macro is implemented in Analog Bits’ proprietary architecture that uses core and EGPFET/EGNFET 1.8V medium-oxide IO devices. The PLL resides inside the IO ring that includes two analog power supply pads, occupying no core area. In order to minimize noise coupling and maximize ease of use, the PLL incorporates a proprietary ESD structure, which is proven in several generations of processes. Eliminating band-gaps and integrating all on-chip components such as capacitors and ESD structures, helps the jitter performance significantly and reduces stand-by power. The PLL macro fits into any standard IO pad pitch and is available for both staggered and in-line IOs.
PLL Operational Range Description Symbol Min Typ Max Units Input Frequency FREF 5 200 MHz Post-Divide Reference Frequency FPFD 5 200 MHz VCO Frequency FVCO 1500 3000 MHz Output Frequency FOUT 25 3000 MHz Output Duty Cycle for FOUT <1500MHz tDO 45 55 % Output Duty Cycle for undivided outputs tDO 40 60 % Lock Time tLOCK 60 µs Total area of macro (excluding bond pad area) A 0.02 sq. mm May vary depending on size of IO slots Chip core area requirement CA 0 sq. mm Total Power IDD 3 mA Operational Voltage (Digital) VDIG 0.9 1.0 1.1 V Operational Voltage (Analog) VANA 1.62 1.8 1.98 V (options available for other IO voltages) Operational Temperature TOP -40 25 125 C Table 1: PLL Operational Range
