The agileLDO_LP is a linear regulator, suitable for use in any low power, low current system and is designed to provide a flexible range of regulated output voltages suitable for ultra-low power systems and near-vt operating modes.
The agileLDO_LP consists of: A voltage reference generator, an error amplifier and a output current source. The regulated output voltage is fed-back into the error amplifier to maintain a constant regulated output over the specified range of input voltages and load currents.
Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable. Our methodology also allows us to quickly re-target our IP to different process options. We support all the major foundries including TSMC, GlobalFoundries, Intel Foundry, Samsung Foundry, UMC and Other Foundries.
Low Power Regulator
Overview
Key Features
- Input voltage range: 1.62 to 1.98V
- Regulated output voltage: 0.825V (typical)
- Active current: 2.5mA (typical) • Powered-down current: 15nA (typical)
- Silicon area: 0.024 mm2 in 16nm technology
- PSRR: @DC: 80dB (typical), @ILOAD = 0.9*ILOAD|MAX), @f = 1MHz: 10dB (typical), @ILOAD = 0.9*ILOAD|MAX)
Benefits
- Low IQ: Low current consumption for power sensitive applications
- Programmable output voltage: Regulated output voltage can be varied allowing near-Vt operation in ultra-low power modes
- Low pin count: Internally decoupled, no requirement for external decoupling capacitor
Block Diagram
Deliverables
- Datasheet
- Testing and Integration Guide
- Verilog Models
- Floorplan (LEF)
- Timing models (LIB)
- Netlist (CDL)
- Layout (GDS)
- Physical Verification Report
- Design Report
Technical Specifications
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