Low-Power ISP

Overview

Key Features

• Input Specification Support:
  • Supports up to 4 independent cameras
  • Supports up to 4 exposures High Dynamic Range (HDR), Digital Overlay (DOL)
  • Supports On-Chip Companded HDR and Sensor linearized HDR
  • Max sensor size per sensor: 16-megapixel
  • Customized low resolution
• Pixel Size and Format Support:
  • Max width / height: 4096 pixels / 2160 lines @60fps.
  • Pixel format RAW (RGGB) and RGBIr (2x2)
  • Linear mode input supports RAW (8, 10, 12, 14, 16, 20 bits)
  • Native (on sensor) companded input
  • On-chip Companded
  • Bypass mode video input (for sensors with internal ISP)
• Image Domain Processing Support:
  • HDR sensor decompanding
  • Multi-exposure fusion
  • Supports 3A (AF, AE, AWB) with metering
  • Gray scale and RGB domain Gamma correction, (On-the-Fly) Dynamic Defect Pixel Correction, Static Defect Pixel Correction: 4K locations, Black Level Correction, Lens shading (vignetting) correction
  • Green channel equalization
  • EW image flip
  • Hue / Saturation Controls
  • Color Noise Reduction, Motion/Texture Aware Noise Reduction(included Spatial and Temporal), Radial shading correction: 128 nodes, Mesh shading correction: 64 x 64, Purple Fringing Correction
  • Static White balance (Gain and Offsets)
  • Dynamic range compression and local tone mapping
  • Demosaic(multi-CFA) with anisotropic sharpening control
  • Chromatic Aberration Correction: Supported for Configuration 1 only
  • 3D Color LUT
  • Crop (per o/p channel)
  • Image mirror and flip
  • Linear matrix color correction
  • RGB Sharpening (per o/p channel)
  • Dehaze
  • Downscaled output maximum resolution(s)
• Video Output Support
  • Output channels: Two – DMA and streaming
  • Color space conversion and Dither (per o/p channel): RGB -> YUV, 4:4:4, 4:2:2, 4:2:0
  • DMA format: Non-planar and semi-planar
  • Video output formatter (per o/p channel)

Benefits

• High performance
• Low latency
• Small area
• High throughput rate up to 600 mega pixel/second
• Fully customizable
• Simple integration process
• FPGA verification support

Deliverables

• Databook
• Encrypted Verilog Model
• Timing Library Model (LIB)
• Library Exchange Format (LEF)
• GDSII Database
• Evaluation Board if Available

Technical Specifications