Low Power Comparator

Overview

The agileCMP_LP is a comparator suitable for use in any low power system. It is designed to provide a flexible range of comparison voltages suitable for many sensor interface designs. The agileCMP_LP consists of a voltage reference generator and comparator set at different threshold levels for multi-level detection and the output is not latched.

Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable. Our methodology also allows us to quickly re-target our IP to different process options. We support all the major foundries including TSMC, GlobalFoundries, Intel Foundry, Samsung Foundry, UMC and Other Foundries.

Key Features

Active current: 2.20mA (typical)
Powered-down current: 9.8nA (typical)
Detection time: 2ms (typical)
Hysteresis: 16.5mV (typical)
Threshold step size: 56.25mV
Threshold accuracy: 4.5mV (max)
Silicon area: 0.013 mm2 in 16nm technology
PSRR: @f < 1MHz: 38.5dB (typical)
@f ≥ 1MHz: 27.9dB (typical)

Benefits

Best-in-class deliverables for easy and seamless integration: our engineers have extensive experience taking complex SoCs from design to mass production
We believe that success is not just measured by delivery of netlist and layout, rather it extends to mass-production and beyond
Automated design procedure accelerates design time and enables quick re-centering with latest PDK updates so you can tape out with the latest foundry models
Tried and tested architecture ensures reliability and functionality

Block Diagram

Applications

IoT, Security, Automotive, AI, SoCs, ASICs

Deliverables

Datasheet
Testing and Integration Guide
Verilog Models
Floorplan (LEF)
Timing models (LIB)
Netlist (CDL)
Layout (GDS)
Physical Verification Report
Design Report

Technical Specifications

Foundry, Node

Samsung

Maturity

Available on request

Availability

Now