The agileCMP_LP is a comparator suitable for use in any low power system. It is designed to provide a flexible range of comparison voltages suitable for many sensor interface designs. The agileCMP_LP consists of a voltage reference generator and comparator set at different threshold levels for multi-level detection and the output is not latched.
Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable. Our methodology also allows us to quickly re-target our IP to different process options. We support all the major foundries including TSMC, GlobalFoundries, Intel Foundry, Samsung Foundry, UMC and Other Foundries.
Low Power Comparator
Overview
Key Features
- Active current: 2.20mA (typical)
- Powered-down current: 9.8nA (typical)
- Detection time: 2ms (typical)
- Hysteresis: 16.5mV (typical)
- Threshold step size: 56.25mV
- Threshold accuracy: 4.5mV (max)
- Silicon area: 0.013 mm2 in 16nm technology
- PSRR: @f < 1MHz: 38.5dB (typical)
- @f ≥ 1MHz: 27.9dB (typical)
Benefits
- Low IQ: Low current consumption for power sensitive applications
- Sensor Interface: Multi-threshold comparison for optimal sensor interfacing
Block Diagram
Deliverables
- Datasheet
- Testing and Integration Guide
- Verilog Models
- Floorplan (LEF)
- Timing models (LIB)
- Netlist (CDL)
- Layout (GDS)
- Physical Verification Report
- Design Report
Technical Specifications
Related IPs
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- I2C Controller IP – Slave, SCL Clock, Parameterized FIFO, APB Bus. For low power requirements in I2C Slave Controller interface to CPU
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- Ultra Low Power Embedded SRAM - TSMC 22ULL