Low noise PLL operating at 1.25GHz and 625MHz (90nm UMC)
Overview
PSI1GLP_U9 is a low jitter PLL operating at 1. 25GHz or 625GHz. PSI1GLP_U9 can be used for a wide range of applications in SERDES transceivers such as GPON, SGMII. It can also be used in many other applications for clock generation.
Key Features
- Low jitter PLL for a wide range of applications
- Output frequencies 1.25GHz and 625MHz
- Reference clock 156.25 MHz with 1/2, 1/4 and 1/8 speed
- Single power supply 0.9-1.3V
- UMC 90nm SP
Technical Specifications
Foundry, Node
UMC 90nm SP
UMC
Silicon Proven:
90nm
G
Related IPs
- Low noise PLL operating at up to 3.25GHz (90nm UMC)
- Analog part of TX+RX lane operating at 1.25G~8Gbps , UMC 28nm HPC Process
- Wide range PLL operating from 135MHz to 945MHz (90nm UMC)
- 2D (vector graphics) & 3D GPU IP A GPU IP combining 3D and 2D rendering features with high performance, low power consumption, and minimum CPU load
- Cap-less 25mA Low Noise LDO, Fujitsu 90nm
- SMIC 90nm 9T Standard Cell Library - RVT, 1.2v operating voltage