The Low Latency Ethernet 10G MAC FPGA IP core (soft IP) offers low round-trip latency, and an efficient resource footprint. The Intellectual Property (IP) core offers programmability of various features listed. This IP can be used in conjunction with the new Multi-Rate PHY FPGA IP core to support the range of 10M/100M/1G to 10G data rates.
The legacy 10G Ethernet MAC FPGA IP core continues to be offered with a full feature set for applications targeting Stratix® V FPGAs, and prior FPGA families.
The 10GE MAC and PHY function with various optional features is also available as hard IP on Stratix® 10 devices with E-tiles. More details can be found at Stratix® 10 FPGA E-Tile Hard IP for Ethernet IP Core.
This FPGA IP core is designed to the IEEE 802.3–2008 Ethernet Standard, available on the IEEE website (www.ieee.org). All Low Latency 10GbE MAC FPGA IP core variations include only MAC in full-duplex mode.
