Low jitter 4.96GHz to 5.6GHz PLL in TSMC N40
Overview
PMCC_PLL5GN40 is a PLL IP block which synthesizes low-jitter (<0.3ps RMS) 4.96GHz to 5.6GHz (5.28GHz typical) clock signals from the 620-700MHz reference clock. The pseudo-differential CMOS outputs are aligned to have ±35ps skew over PVT. The block is powered from the 0.9V (core) and 1.8V supply voltages. Silicon proven on 2 ASICs. Can be modified as per customer specifications.
Key Features
- Low RJ output – 0.3ps RMS for the primary 5GHz output.
- A built-in bandgap block for the generation of reference voltages/currents.
- An output clock duty cycle within 50±3% range.
- Jitter peaking <1dB.
- The embedded FSM for the PLL auto-tune with a lock-detection indicator.
- Power consumption of 25mW.
- Total on-chip area 0.42mm2.
Benefits
- The PLL IP block provides high-accuracy clock signals with predictable timing constrains.
Applications
- Any ASIC in the TSMC 40G process.
- Can be modified to fit any application.
Deliverables
- LEF view
- Verilog (.v)
- Liberty file (.lib)
- GDSII
- CDL/Spice netlist for LVS
Technical Specifications
Foundry, Node
TSMC, 40 nm
Maturity
Silicon proven on 2 ASICs
Availability
Now
TSMC
In Production:
40nm
G
Pre-Silicon: 40nm G
Silicon Proven: 40nm G
Pre-Silicon: 40nm G
Silicon Proven: 40nm G
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