Low Dropout (LDO) Capless Regulator 250mA - TSMC 7FF

Overview

1-VIA’s Linear Low-Dropout (LDO) voltage regulator IP is a capless LDO regulator which provides programmable precise voltage regulation across a wide range of input and output voltages. The LDO also has the capability to provide a wide range of output load current, 0-250mA, whilst being stable and maintaining an extremely low load transient and line transient regulation responses.

The regulator architecture provides high power supply rejection and low noise making it suitable for analog and RF applications.

Key Features

  • Low start-up time
  • Low power
  • High PSRR
  • Low load transient response
  • Low line transient response
  • Capless LDO

Benefits

  • Low start-up time
  • Small area
  • High power efficiency
  • Stable across a wide load capacitor range (up to 10nF)

Applications

  • Artificial Intelligence (AI)
  • Internet of Things (IoT)
  • Medical
  • Analogue-to-Digital Converter (ADC)
  • RF ASICs
  • Automotive
  • Wireless
  • Digital-to-Analog Converter (DAC)
  • Mixed-signal ASICs
  • SoCs

Deliverables

  • Datasheet
  • Characterization report
  • Layout view (GDSII)
  • Abstract view (LEF)
  • Behavioural model (VerilogA)
  • Integration guidelines and support

Technical Specifications

Foundry, Node
TSMC 7FF
TSMC
Pre-Silicon: 7nm
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Semiconductor IP