The Link core is a functional block available for insertion into a customer's ASIC design, which supports the IEEE 1394a - 2000 Draft specifications for a high - speed serial bus. The SI16FWA20 Link core is implemented using VHDL synthesizable code to provide portability across Silicon Interfaces Gate Array and Cell - Based ASIC technologies.
SI16FWA20, 1394a - 2000 Link Layer Controller Core provides data packet delivery service for Asynchronous and Isochronous (real - time) data transmission. It performs arbitration request, packet generation and checking as well as data and acknowledgement transmission. Packet Generation includes setting up of Packet Header, Address, Data CRC, Packet Channel, Destination Address and Transaction Code. Silicon Interfaces® Link Layer Controller core also provides complete support for bus Cycle Master and cycle control operation. SI16FWA20 is designed to support 100, 200 and 400 Mbps transmission, when used with the appropriate external Physical Layer device. This depends upon the speed provided with a 2 bit, 4 bit or 8 bit interface, which does not require special high - speed buffers. Besides, this version supports generation of LPS (Link Power Status) signal, based on the current mode in which the device operates (Differentiated or Undifferentiated).
SI16FWA20 highly integrated single - chip core is Silicon Interfaces® Intellectual Property and represents the company's proven Link Layer design experience as well as expertise in the field of complex designs. The complete modular design of SI16FWA20 core facilitates easy customization in order to include value added distinguished features.
Product Specifications :
- Modes : Asynchronous, Asynchronous Stream and Isochronous Stream
- Core : Fully synthesizable Register Transfer Level (RTL) VHDL
- Test Environment : Reusable Verilog with abundant scenarios
- Targeted FPGA : Xilinx Spartan-6 / Virtex-6
- Clock Frequency : 50 MHz
