Linear Regulator IP, Output: 2.8V/20mA, UMC 55nm SP process
Overview
3.3V to 2.8V with 20mA driving capability, Linear Regulator, UMC 55nm SP/RVT Logic process.
Technical Specifications
Foundry, Node
UMC 55nm SP
UMC
Pre-Silicon:
55nm
Related IPs
- Single Port SRAM Compiler IP, UMC 65nm SP process
- Linear Low-Dropout Regulator (Output Voltage 0.9V)
- Linear Low-Dropout Regulator (Output Voltage 0.6V)
- On-Chip IO to Core Voltage Buck Regulator on UMC 55nm ULP
- Linear Voltage Regulator - High Input Voltage (30V), Output Load up to 5mA
- Programmable LDO voltage regulator (output voltage 2.5 V to 2.7 V)